Outphasing power amplification is highly effective power amplification using a class-D power amplifier (see, e.g., Patent Document 1).
An outline of the outphasing power amplification will be described with reference to FIG. 4. FIG. 4 shows an outphasing power amplifying device using a full-bridge class-D power amplifier.
In FIG. 4, switching signals generated based on modulated wave signals to be transmitted are inputted to four gate terminals G1 to G4. As a result, a square-wave-shaped signal is outputted as an output of a class-D power amplifier 101. This output signal contains a desired modulated wave signal and a high frequency component. Therefore, filtering is performed at a subsequent stage of the class-D power amplifier 101 by using a filter 102 and the desired modulated wave signal is extracted.
Hereinafter, switching signals inputted to four gate terminals G1 to G4 shown in FIG. 4 will be described with reference to FIG. 5. FIG. 5 shows examples of the switching signals applied to the gate terminals G1 to G4. In FIG. 5, (a) shows a switching signal inputted to the gate terminal G1, (b) shows a switching signal inputted into the gate terminal G3, (c) shows an output signal of an amplifier at A point in FIG. 4, and (d) shows a filter output signal at B point in FIG. 4.
Here, the case of AM modulation is illustrated for simple description. A notation T in the drawing indicates a cycle of a carrier wave.
As shown in FIG. 5, at A point in FIG. 4, the ouput signal becomes positive when G1 and G4 are ON and G3 and G2 are OFF, whereas the ouput signal becomes negative when G1 and G4 are OFF and G3 and G2 are ON. By controlling the change timing of G1 and G2 (=−G1) and that of G3 and G4 (=−G3) based on the above features, the waveform of the square-wave-shaped signal at A point is changed.
Next, a method for generating the switching signals inputted to the four gate terminals G1 to G4 shown in FIG. 4 will be described with reference to FIG. 6. FIG. 6 is a block diagram showing a configuration of a switching signal generating circuit for generating switching signals applied to the four gate terminals G1 to G4 shown in FIG. 4.
As shown in FIG. 6, a conventional switching signal generating circuit includes a modulation unit 1, an interpolation unit 2, an amplitude calculation unit 3, an amplitude-phase conversion unit 4, a multiplier 5, a phase calculation unit 6, an adder 7, a normalization unit 18, an ON period calculation unit 19, a quantization unit 20, a counter 21, a comparison unit 22 and an inversion unit 23.
In the conventional switching signal generating circuit, first, the modulation unit 1 generates a modulated signal to be transmitted and the interpolation unit 2 upsamples the modulated signal to a rate of a carrier wave frequency (or a frequency close thereto).
After the upsampling in the interpolation unit 2, the amplitude calculation unit 3 and the phase calculation unit 6 converts each sample into a polar form (amplitude value, phase value).
After the conversion into the polar form, the amplitude-phase conversion unit 4 converts the amplitude value into an angle value ϕ. The relative relationship of the control pulses for G1 and G3 is controlled by the angle value ϕ. Further, the relative relationship is controlled by advancing the control pulse for G1 by ϕ/2 and delaying the control pulse for G3 by ϕ/2. Therefore, the angle value ϕ is reduced to a half by the multiplier 5.
Next, the adder 7 generates a phase of a control pulse for G1 (θ+ϕ/2) and a phase of a control pulse for G3 (θ−ϕ/2+π) by using the angle value ϕ/2 obtained from the multiplier 5 and the phase value θ obtained from the phase calculation unit 6.
The phases generated for G1 and G3 are converted to pulse signals for switching by the normalization unit 18, the ON period calculation unit 19, the quantization unit 20, the counter 21, the comparison unit 22 and the inversion unit 23.
The counter 21 updates the value at a cycle sufficiently shorter than the carrier wave cycle and the value of the counter 21 returns to the original value at a carrier wave cycle. (For example, the counter 21 repeats an operation of counting up the value from 0 to 63 by one at a 1/64 cycle of the carrier wave cycle and returning the value to 0.)
A reference for determining the count value is calculated by the normalization unit 18, the ON period calculation unit 19 and the quantization unit 20. First, the normalization unit 18 normalizes a phase of 0 to 2π to a range of 0 to 1. Next, the ON period calculation unit 19 determines an ON period within a range from 0 to 1. (For example, when θ=0 and ϕ/2=0, an ON period for G1 and G2 (=−G1) becomes 0 to 0.5 and an ON period for G3 and G4 (=−G3) becomes 0.5 to 1; and when θ=0 and ϕ/2=π/4, an ON period for G1 and G2 (=−G1) becomes 0 to 0.375 and 0.875 to 1 and an ON period for G3 and G4 (=−G3) becomes 0 to 0.125 and 0.625 to 1.) The quantization unit 20 quantizes the determination reference value based on a word length of a value of the counter. (For example, in comparison with the six-bit counter (0 to 63), an output of the ON period calculation unit 19 is multiplied by 64 and rounded off to the nearest tenth.) Accordingly, the on/off of the respective switching signals are switched based on the value of the counter 21.
Patent Document 1: Japanese Patent Application Publication No. 2004-48703
In a conventional case, the accuracy of on/off timing of a switching signal is affected by processing resolution in the carrier wave cycle T. Specifically, the available number of timings is limited to the number of states expressed by the counter 21 in FIG. 6 and the quantization in a time axis direction is additionally required during the control. As a result of the quantization, a difference between an output waveform of a class-D power amplifier and an output waveform obtained from ideal switching is generated. The effect of the difference is monitored as a noise in and out of a band of a modulated wave even after final filtering and various characteristics such as spurious characteristics in the out-of-band region, EVM (Error Vector Magnitude) and the like deteriorate.
Therefore, the updating process in the counter 21 and the comparison process in the comparison unit 22 shown in FIG. 6 need to be performed by a sufficiently high operating clock which can achieve acceptably low noise level.
However, at the same time, it is not possible to unconditionally increase the operating clock of the digital circuit due to the limit of the radio frequency. For example, the logic has an operating clock of 6.4 GHz only by controlling the switching signal by the resolution of 1/64 of the cycle of 100 MHz on the assumption that the radio frequency (carrier wave frequency) is 100 MHz. When the high operating clock is necessary, it is difficult to realize hardware.